The present invention relates to a method of manufacturing semiconductor devices, and is particularly useful in manufacturing high density semiconductor devices with submicron design features. The invention is particularly applicable in manufacturing semiconductor devices having features in the deep submicron range with reduced critical dimensions.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active regions typically comprise source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each circuit component.
The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, forming the active regions. One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then filled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure.
A typical method of STI formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride, e.g., silicon nitride, polish stop layer thereon. A photoresist mask is then applied to the nitride layer, and a pattern defining the trench areas is formed in the photoresist mask. This is accomplished by a photolithographic process in which selected areas of the photoresist are exposed to light via a mask or reticle and thereafter developed to form apertures extending to and exposing portions of the underlying nitride layer. The exposed portions of the nitride layer are etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped from the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control silicon-silicon oxide interface quality. The trench is then filled with an insulating material (or xe2x80x9ctrench fillxe2x80x9d), such as silicon dioxide derived from tetraethylorthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop, and the remaining nitride and pad oxide are stripped off from the active areas to complete the trench isolation structure.
Next a gate oxide layer is formed over the STI structure by thermal oxidation, followed by application of a polysilicon layer and another photoresist layer. The polysilicon layer is etched to form the gate electrode. Patterning of the polysilicon layer is carried out by a photolithographic process similar to that described above in connection with STI formation; that is, the photoresist layer is exposed to light via a mask or reticle and developed to form a pattern exposing portions of the underlying polysilicon layer, which are then etched.
The photoresist patterning must be highly precise to enable accurate etching of the underlying layer. For example, random variations in pattern dimensions can result in unacceptable variation in gate electrode width and high electrode failure rate.
As used herein, the term xe2x80x9ccritical dimensionxe2x80x9d or xe2x80x9cCDxe2x80x9d refers to the design rule for features on a semiconductor substrate such as a gate electrode. Because these features are formed by patterns on the photoresist, CD also reflects the precision needed for forming the pattern in the photoresist. Current generation semiconductor technologies have a CD of 0.25 microns or less, in some instances as low as 0.15 microns or less, or even as low as 0.12 microns or less. A CD of 0.12 microns means that this is the minimum width required for a feature, such as a gate electrode, to achieve acceptable quality control and reject rates. The lower the CD, the more densely packed the features on a semiconductor substrate can be.
Critical dimension accuracy of photolithographically formed features is adversely affected (i.e., increased or decreased) by high reflectivity of the photoresist layer and the underlying layer, such as an oxide or polysilicon layer. Both layers are substantially transparent, and, hence, during the exposure step of the photolithography process, light penetrates through these layers and is reflected back. This increases the exposure area on the photoresist, resulting in correspondingly larger apertures. Normally, the exposure level can be adjusted to account for a constant reflectivity level from the photoresist and underlying layers. However, the amount of reflectivity can vary with layer thickness and refractive index. Due to the refractive index mismatch of the photoresist and underlying layers, normal variations in layer thickness have a large effect on reflectivity. Thus small thickness variations in the photoresist or underlying layer result in a large xe2x80x9cswing effectxe2x80x9d, defined as the change in critical dimension as a function of layer thickness.
CD variation as function of layer thickness can be seen with reference to FIGS. 1-5. FIG. 1 illustrates a semiconductor device 10 provided with source/drain regions 12, channel region 14, gate oxide layer 16, and gate electrode 18. The gate electrode 18 of FIG. 1 has the proper dimensions, i.e., its width extends between the source drain regions 12 above the channel region 14. FIG. 2 illustrates the formation of aperture 20 in a photoresist layer used in the formation of a gate electrode. In FIGS. 2-5, source/drain regions 12 are depicted using dotted lines, because these areas are typically formed subsequent to gate electrode formation. The photoresist layer 22 and the polysilicon layer 24 have a variable thickness (exaggerated in FIG. 2) which causes variation in the reflectivity during the exposure step. Because of this, the apertures 20 can vary in size. As shown in FIG. 2, apertures 20 are smaller because the polysilicon layer and/or the photoresist layer is thinner than anticipated in the exposed regions. This results in a gate electrode 26 as shown in FIG. 3 having a width greater than the design specification.
The opposite effect is shown in FIGS. 4 and 5. In FIG. 4, one or both of the photoresist or polysilicon layers are thicker in the regions exposed to light in the lithographic process. This results in larger aperture 28 and subsequently a smaller gate electrode 30 after the etching process. Thus, the semiconductor device is not within design specification.
One method of reducing reflectivity and consequently CD variation is to provide an antireflective coating between the underlying layer and the photoresist layer. Such coatings reduce the amount of light reflected back into the photoresist layer by partially absorbing the light after it passes through the photoresist. However, antireflective coatings do not completely eliminate swing effects since some light is still reflected and therefore effects photoresist aperture size and etch areas on the polysilicon layer. Moreover, they require an additional manufacturing step to apply and can themselves have an adverse impact on failure rate.
Hence, there remains a need in the art for a method for further reducing CD swing effect to allow more precise control of feature dimension and hence a reduction in CD variation.
It is accordingly an aspect of the invention to provide a method for manufacturing a semiconductor device that allows more precise control of critical dimension. It is another aspect of the invention to provide a method of manufacturing a semiconductor device that does not require the application of additional layers to the device to reduce reflectivity.
These aspects and others set forth hereinbelow are achieved by method of manufacturing a semiconductor device, the method comprising forming a first layer on a silicon substrate; applying a photoresist layer on the first layer; measuring the reflectivity of light passing through a portion of the photoresist layer and of a corresponding portion of the first layer; selecting a photolithographic exposure level based on the measured reflectivity; and exposing said portion of the photoresist layer at the selected exposure level. The process of measuring the reflectivity of a portion of the layers, selecting the proper exposure level and then exposing the photoresist portion, is repeated for different portions of the photoresist until the entire photoresist is exposed. Thereafter, the photoresist is developed and the underlying layer etched, thereby forming features having substantially less critical dimension variation than features formed by conventional processes.